(1) Field of the Invention
This invention relates to the field of semiconductor manufacturing, and more specifically to an improved method for depositing amorphous silicon thin film on a semiconductor substrate.
(2) Description of the Prior Art
Thin films of amorphous and polycrystalline silicon are widely used in semiconductor manufacturing. For example, amorphous silicon can be used for the formation at the gate of CMOS structures for application in the dual gate process since the amorphous silicon can effectively reduce the Boron (B) penetration from the gate to the device region. Doped polycrystalline silicon can be used to form interconnects, gate electrodes, emitter structures and resistors. These silicon thin films are typically formed by LPCVD (low pressure chemical vapor deposition) by decomposition of a silicon gas such as silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6). Doping can also be accomplished in the gas phase by introducing a dopant gas such as diborane (B.sub.2 H.sub.6), arsine (AsH.sub.3) or phosphine (PH.sub.3). The deposition temperature during LPCV is typically from 500 degrees C. to 675 degrees C. and the pressure is typically from 200 mTorr to 2 Torr. The crystalline structure of the `as deposited` film is largely a function of the deposition temperature. At temperatures below about 550 degrees C. the `as deposited` films have an amorphous structure. At temperatures between about 550 degrees C. and 580 degrees C. there is a transition between amorphous silicon and polycrystalline silicon. Hemispherical grain (HSG) polysilicon is typically grown in this transitional range. At temperatures above about 580 degrees C. the `as deposited` films have a polycrystalline structure.
In addition to LPCVD, there are other methods for depositing thin films of amorphous and polycrystalline silicon. One such method is plasma-enhanced chemical vapor deposition (PECVD) and rf induced glow discharge is used to transfer energy into the reactant gases. Advantages of PECVD include lower substrate temperatures and higher deposition rates. A representative temperature range for PECVD of silicon thin films is about 350 degrees C. to 450 degrees C. Another method of depositing amorphous and polycrystalline silicon thin films is RTCVD (rapid thermal chemical vapor deposition). With RTCVD the structure is typically rapidly heated by lamps and the reactant gases are introduced.
One problem that occurs during deposition of in-situ doped amorphous or polycrystalline silicon thin film is the degradation of the underlying substrate film by reaction of the dopant species with contaminants on the substrate. Specifically, an underlying substrate can be attacked by acidic gasses formed by the dopant species during the deposition process. For example, with a phosphine (PH.sub.3) dopant, phosphoric acid (H.sub.3 PO.sub.4) can be generated by the reactor of phosphine (PH.sub.3) with oxygen (O.sub.2) or water (HO.sub.2) present in the substrate or in the reaction chamber. Phosphoric acid is highly corrosive and can attack an underlying film such as silicon nitride (Si.sub.3 N.sub.4).
These problems are compounded by the increased use of HSG or rugged polysilicon. This type of polysilicon increases the surface area and the `trapping` area on the substrate for contaminants. In addition, during CVD of silicon, the deposition process does not occur immediately upon introduction of the reactant gasses. This gives the reactant gasses time to combine with corrosive by-products, which can attack the unprotected substrate.
In view of the foregoing, it is the objective of the present invention to provide an improved method for depositing doped amorphous and polycrystalline silicon thin films without degradation of the underlying substrate film.
In the conventional process of depositing amorphous silicon film, a pressure of 11 pa is used while the temperature is set at 550 degrees C. The present invention provides for adjusting these two processing parameters in order to obtain optimum processing results in depositing amorphous silicon.
U.S. Pat. No. 5,677,211 (Kaneko), U.S. Pat. No. 5,504,019 (Miyasakaet al.), U.S. Pat. No. 5,652,156 (Liao et al.), U.S. Pat. No. 5,767,004 (Balasubramanian et al.) and U.S. Pat. No. 5,789,030 (Rolfson) shows amorphous silicon deposition techniques.